The present invention generally relates to semiconductor devices and method of producing the same, and more particularly to a semiconductor device having a stacked structure made up of conductor and insulator layers such as a stacked type capacitor, and to a method of producing such a semiconductor device.
Recently, in DRAMs which have become important in information processing systems such as computers, the formation of a capacitor having a large storage capacitance has become an important problem to be solved. However, as the size of the DRAM decreases with higher integration density, the area of one cell inevitably decreases. For this reason, three dimensional cells such as the stacked type capacitor and the trench type capacitor have been proposed for the purpose of securing a sufficient storage capacitance within a limited area. A fin type capacitor which is a kind of stacked type capacitor seems promising in that a storage capacitor of a large capacity DRAM having a memory capacity of 16 M or greater can be realized. For example, the fin type capacitor is proposed in IEDM Technical Digest, 1988, p.592.
FIG. 1 (A) through (C) are diagrams explaining the construction of a conventional fin type capacitor.
In FIG. 1, there are shown a semiconductor substrate 21, a LOCOS oxide layer 22, a gate oxide layer 23, a gate electrode (word line) 24, a source region 25, a drain region 26, a word line 27 of another cell, an interlayer insulator 28, fin type storage electrodes 29-1, 29-2 and 29-3, a dielectric layer 30, and an opposing electrode 31.
FIG. 1 (A) shows the construction of one cell of a DRAM having a fin type capacitor which has one fin type storage electrode.
In this DRAM, the LOCOS oxide layer 22 which sections an element forming region is formed on the semiconductor substrate 21, and the gate oxide layer 23 is formed on this element forming region, as shown in FIG. 1 (A). The gate electrode 24 which becomes the word line is formed on the gate oxide layer 23, and the word line 27 of the other cell is formed on the LOCOS oxide layer 22. The source region 25 and the drain region 26 are formed in self-alignment to the gate electrode 24, and the interlayer insulator 28 is formed thereon. One fin type storage electrode 29-1 is formed at an opening which is formed above the drain region 26. The dielectric layer 30 is formed on the surface of the fin type storage electrode 29-1, and the opposing electrode 31 is formed in contact with the dielectric layer 30.
When the fin type capacitor having this fin type storage electrode is used, it is possible to form a capacitance at the top and bottom surfaces of the fin type storage electrode, thereby making it possible to obtain a large storage capacitance with the limited area occupied by the cell.
FIG. 1 (B) shows the construction of a fin type capacitor having two fin type storage electrodes, and FIG. 1 (C) shows the construction of a fin type capacitor having three fin type storage electrodes. As shown in these figures, it is possible to increase the number of fin type storage electrodes to two (29-1, 29-2), three (29-1, 29-2, 29-3), . . . Hence, it is possible to obtain a sufficient storage capacitance even if the cell area becomes small due to the high integration density.
In FIG. 1 (A), (B) and (C), the illustration of the bit line is omitted.
FIG. 2 shows a plan view of a DRAM having the conventional fin type capacitor.
In FIG. 2, there are shown word lines 44 and 47, a first opening 49, a bit line 50, a second opening 55, and a second polysilicon layer 56.
The cell structure of this DRAM will be described in conjunction with the production method with reference to FIGS. 3 and 4, but the bit line 50 extends in a horizontal direction and the word lines 44 and 47 extend in a vertical direction. A rectangular region indicated by a dotted line shows one cell of the DRAM. Lines X-X', Y-Y' and Z-Z' in FIG. 2 shows parts where the cross sections are taken in the cross sectional views which will be described later.
FIG. 3 (A) through (E) and FIG. 4 (A) through (C) are diagrams for explaining the processes of producing the DRAM having the conventional fin type capacitor.
In these figures, there are shown a semiconductor substrate 41, a LOCOS oxide layer 42, a gate oxide layer 43, a gate electrode 44, a source region 45, a drain region 46, a word line 47 of another cell, an interlayer insulator 48, a first opening 49, a bit line 50, a Si.sub.3 N.sub.4 layer 51, a first SiO.sub.2 layer 52, a first polysilicon layer 53, a second SiO.sub.2 layer 54, a second opening 55, a second polysilicon layer 56, a dielectric layer 57, and an opposing electrode 58.
A description will be given of the conventional method of producing the fin type capacitor having two fins, with reference to these explanatory diagrams. These explanatory diagrams show the cross section along the line X-X' in FIG. 2 which shows the plan view of a part of the DRAM.
First Process (Refer to FIG. 3(A))
The surface of the p-type semiconductor substrate 41 is thermally oxidized to form the LOCOS oxide layer 42 which sections the element region. The gate oxide layer 43 is formed on this element region by a thermal oxidation, and a polysilicon layer is formed thereon by a CVD. The polysilicon layer is patterned to form the gate electrode 44 which also becomes the word line, and the source region 45 and the drain region 46 are formed in self-alignment to the gate electrode 44. In addition, the word line 47 of the other cell is formed on the LOCOS oxide layer 42 at the same time as the gate electrode 44.
Second Process (Refer to FIG. 3(B))
The interlayer insulator 48 which is made up of SiO.sub.2 is deposited by CVD to cover the entire surface, and the first opening 49 is provided at the contact part of the bit line.
Third Process (Refer to FIG. 3(C))
A stacked layer of polysilicon layer and tungsten silicide (WSi) is deposited by CVD on the entire surface including the first opening 49. This stacked layer is patterned to form the bit line 50 which is connected to the source region 45 within the first opening 49.
Fourth Process (Refer to FIG. 3(D))
The Si.sub.3 N.sub.4 layer 51, the first SiO.sub.2 layer 52, the first polysilicon layer 53, and the second SiO.sub.2 layer 54 are successively deposited thereon by CVD.
Fifth Process (Refer to FIG. 3(E))
The second SiO.sub.2 layer 54, the first polysilicon layer 53, the first SiO.sub.2 layer 52, the Si.sub.3 N.sub.4 layer 51, the interlayer insulator 48, and the gate oxide layer 43 on the drain region 46 are etched using the same resist mask, so as to form the second opening 55 at the storage electrode contact part.
Sixth Process (Refer to FIG. 4(A))
The second polysilicon layer 56 is formed by CVD on the entire surface including the second opening 55. Then, the second polysilicon layer 56, the second SiO.sub.2 layer 54 and the first polysilicon layer 53 are successively etched to pattern the same to a predetermined shape.
Seventh Process (Refer to FIG. 4(B))
The second SiO.sub.2 layer 54 and the first SiO.sub.2 layer 52 are etched by an isotropic wet etching using a HF solution, so as to form fin type storage electrodes made up of the first and second polysilicon layers 53 and 56. The Si.sub.3 N.sub.4 layer 51 acts as a stopper with respect to the etching using HF (hydrofluoric acid).
Eighth Process (Refer to FIG. 4 (C))
The dielectric layer 57 is formed on the surfaces of the fin type storage electrodes which are made up of the first and second polysilicon layers 53 and 56, and a polysilicon layer is deposited by CVD to form the opposing electrode 58 and complete the fin type capacitor cell.
Thereafter, a BPSG layer is formed by a normal process, and the necessary aluminum wiring is made thereon.
However, according to the conventional method described above, the following problems are generated.
1. A short-circuit may occur between the conductor layers.
FIG. 5 is a diagram for explaining the process of patterning the storage electrode by the conventional method. FIG. 5 shows the cross section along the line Z-Z' in FIG. 2. In FIG. 5, there are shown the semiconductor substrate 41, the LOCOS oxide layer 42, the interlayer insulator 48, the bit line 50, the Si.sub.3 N.sub.4 layer 51, the first SiO.sub.2 layer 52, the first polysilicon layer 53, the second SiO.sub.2 layer 54, and the second polysilicon layer 56.
FIG. 5 (A) shows a stage where the LOCOS oxide layer 42 is formed on the semiconductor layer 41, the interlayer insulator 48 is formed, the bit line 50 is formed, and the Si.sub.3 N.sub.4 layer 51, the first SiO.sub.2 layer 52, the first polysilicon layer 53, the second SiO.sub.2 layer 54 and the second polysilicon layer 56 are formed thereon.
FIG. 5 (B) shows a state where the uppermost second polysilicon layer 56 is removed. Since this figure is the cross section along the line Z-Z' in FIG. 2, the second polysilicon layer 56 is to be eliminated completely. However, since the second polysilicon layer 56 includes a stepped part, the second polysilicon layer 56 partially remains on the sidewall portion of the stepped part.
FIG. 5 (C) shows a state where the first polysilicon layer 53 is removed. In this case, since the first polysilicon layer 53 includes a stepped part, the first polysilicon layer 53 partially remains at the sidewall portion of the stepped part.
If the second polysilicon layer 56 or the first polysilicon layer 53 remains, there is a possibility of the adjacent storage electrodes becoming short-circuited by the etching residue of the polysilicon which is lifted off when the SiO.sub.2 layers 52 and 54 and the like are removed at the subsequent processes.
In order to eliminate the above described etching residue, the etching time is normally made longer when etching the polysilicon by RIE, so as to make the so-called over-etching. However, if the over-etching is excessively made, too much of the flat portion becomes etched and the underlayer will be damaged. On the other hand, the etching is normally made using a resist mask which is patterned, and there is also a problem in that the resist will not be usable as a mask if the resist is damaged by the over-etching. Furthermore, the so-called etching shift in which the line width becomes narrow will occur when the over-etching is made, and there is still another problem in that the obtained pattern becomes smaller than the desired pattern.
On the other hand, the etching time naturally increases when the over-etching is made, and the production cost of the semiconductor device is increase thereby. In addition, when forming the fin type capacitor having a plurality of fins, it is necessary to alternately make the selective etching of the conductor layer and the insulator layer, and the total etching time is considerably increased when the over-etching is made because the number of etching processes is quite large to start with.
2. The thickness of the photoresist layer will become non-uniform.
FIG. 6 (A) and (B) is a diagram for explaining the conventional photolithography process for forming a contact hole. In this figure, there are shown the semiconductor substrate 41, the LOCOS oxide layer 42, the gate oxide layer 43, the gate electrode 44, the source region 45, the drain region 46, the word line 47 of the other cell, the interlayer insulator 48, the first opening 49, the Si.sub.3 N.sub.4 layer 51, the first SiO.sub.2 layer 52, the first polysilicon layer 53, the second SiO.sub.2 layer 54, a photoresist layer 59, and a photomask 60.
FIG. 6 (A) shows the cross section along the line X-X' in FIG. 2. The LOCOS oxide layer 42 is formed on the semiconductor substrate 41, the gate oxide layer 43 is formed, and the gate electrode 44 and the word line 47 of the other cell are formed. Then, the interlayer insulator 48 is formed, and the bit line 50 is formed. The Si.sub.3 N.sub.4 layer 51, the first SiO.sub.2 layer 52, the first polysilicon layer 53, the second SiO.sub.2 layer 54, and the second polysilicon layer 56 are formed thereon. The photoresist layer 59 is formed on top, and an exposure is made using the photomask 60.
FIG. 6 (B) shows the cross section along the line Y-Y' in FIG. 2. The LOCOS oxide layer 42 is formed on the semiconductor layer 41, the gate oxide layer 43 and the interlayer insulator 48 are formed, and the bit line 50 is formed. Then, the Si.sub.3 N.sub.4 layer 51, the first SiO.sub.2 layer 52, the first polysilicon layer 53, and the second SiO.sub.2 layer 54 are formed thereon. The photoresist layer 59 is formed on top, and an exposure is made using the photomask 60.
Hence, according to the conventional process of producing the fin type storage electrode, the second SiO.sub.2 layer 54, the first polysilicon layer 53, the first SiO.sub.2 layer 52, the Si.sub.3 N.sub.4 layer 51, the interlayer insulator 48 and the gate oxide layer 43 are etched by the photolithography technique to form the opening which is used to form the fin type storage electrode. But since a stepped part exists on the surface of the uppermost second SiO.sub.2 layer 54 when forming this opening, the thickness of the photoresist layer 59 which is spin-coated on the uppermost second SiO.sub.2 layer 54 becomes extremely non-uniform. As a result, it is difficult to accurately form a fine contact opening, and there is a problem in that the production yield is deteriorated thereby.
3. A disconnection easily occurs at the contact hole.
In FIG. 4 (B), when forming the fin type storage electrodes made up of the first and second polysilicon layers 53 and 56, the isotropic etching using the HF solution is made to remove the SiO.sub.2 layers 54 and 52. When making this isotropic etching, the Si.sub.3 N.sub.4 layer 51 which isolates the bit line 50 acts as a stopper (mask) with respect to the HF solution, and the etching of the bit line 50 will not occur even if submerged in the HF solution. However, the existence of the Si.sub.3 N.sub.4 layer 51 introduces a problem shown in FIG. 7.
FIG. 7 shows a cross section of a peripheral circuit part of the conventional memory described in conjunction with FIGS. 3 and 4. In FIG. 7, those parts which are the same as those corresponding parts in FIGS. 3 and 4 are designated by the same reference numerals, and a description thereof will be omitted. In FIG. 7, there are shown an impurity diffusion layer 37, a BPSG layer 38, and an Al layer 39.
When a contact hole shown in FIG. 7 (A) is formed and the Al layer 39 is formed thereafter, it is necessary to stabilize the contact resistance between the impurity diffusion layer 37 and the Al layer 39. Normally, a pre-process is made using a solution of the HF system before forming the Al layer 39, so as to remove the natural oxide layer on the impurity diffusion layer 37.
However, if such a pre-process is made, the BPSG layer 38 and the SiO.sub.2 layer 48 will recede by being etched by the HF solution, but the Si.sub.3 N.sub.4 will not be etched. As a result, only the Si.sub.3 N.sub.4 layer 51 projects within the contact hole as shown in FIG. 7 (B).
When the Al layer 39 is formed by sputtering over a contact hole having such a shape, there is a problem in that a disconnection of the Al layer 39 easily occurs at a part A as shown in FIG. 7 (C).